1. Field of the Invention
This invention relates to a treatment process for an intrinsic gettering semiconductor wafer.
2. Description of the Prior Art
Nowadays, intrinsic gettering wafers (IG wafer), are often used for high density integrated circuit devices. An IG wafer has the structure as shown in FIG. 1. In this structure, one region (2) which includes no small crystal defects is formed in the surface of the wafer (1) and another region (3) which includes many small defects is formed in the interior of the wafer. By small defects is meant all defects, including combinations like SiO.sub.2, dislocations, stacking faults in the crystal, etc. When a semiconductor device is manufactured using an IG wafer, impurities (4) in the surface region (2) are gettered to the internal region (3) in a heating step and undesirable carriers (5) produced in the surface region (2) recombine in the internal region (3) as shown in FIG. 2.
FIG. 2 shows a completed memory device. A thick SiO.sub.2 field layer (6) is formed on a P type semiconductor substrate (1) of an IG wafer made of Si. An electrode (7) made of polycrystalline Si is formed on a thin SiO.sub.2 layer (8) and the thick field layer (6). A capacitance is constituted between the electrode (7) and the substrate (1). A transfer gate electrode (9) made of polycrystalline Si is formed on a gate insulation layer (10) made of SiO.sub.2 and an insulation layer (11) made of SiO.sub.2. By applying a voltage to the transfer gate electrode (9), an inversion layer is induced in the surface region under the gate insulation layer (11). Wiring layers (13) are connected to the transfer gate electrode (9), the electrode (7) and a N.sup.+ layer (14) formed in the surface region (2) through holes formed in the insulation layer (12). In this device, the undesirable carriers (5) often will be produced in an operating srate, and may become the cause of misoperation of the device. The undesirable carriers (5) are produced by .alpha.-rays incident from the outside, by a breakdown in the PN-junction and so on. But if an IG wafer is used, the undesirable carriers (5) recombine in the internal region (3).
In a prior fabrication technique, an IG wafer is manufactured as follows. At first, a semiconductor wafer (15) made of Si including oxygen is prepared as shown in FIG. 3. Oxygen in a concentration of 10.sup.18 cm.sup.-3 is included in the wafer (15). Small defects will be formed positively by the oxygen in the following steps. The wafer (15) is heated in an oxidation atmosphere of about 800.degree. C. for about 2 to 5 hours. Then, the supersaturated oxygen in the wafer (15) diffuses and cores (16) of small defects are produced as shown in FIG. 4. Next, this wafer (15) is heated again in an oxidation atmosphere of about 1100.degree. C. for abour 4 hours. Then, oxygen and small defects (16) in the surface region of the wafer (15) are out diffused because of the high temperature. A region (17) including no small defects is formed in the surface of the wafer (15), and another region (18) including many small defects is formed in the interior of the wafer (15) as shown in FIG. 5. The region (17) is generally deeper than 5 .mu.m because of the high temperature and long heating process. In an experiment, region (17) was formed 20 .mu.m deep in the case of a wafer having a thickness of 600 .mu.m. It is difficult to control precisely the depth of the region (17) because of the long heating treatment. A depth of 20 .mu.m is too deep for application of the device as a memory device, for high density inregrated circuits and so on, because the active region of these devices is generally much thinner than 5 .mu.m. Also, the wafer (15) may sometimes bend because of the long high temperature treatment and the thick defect-region (18) having a thermal expansion coefficient different from that of the region (17). Bending of the wafer (15) will produce other undesirable small defects in the surface region (17). Additionally, impurities such as Fe, Cu, Ag and so on may be introduced in the wafer (15) during the high temperature treatment. As the long heating treatment is performed in an oxidation atmosphere in order to prevent contamination, an insulation layer of SiO.sub.2 is formed on the surface of the wafer (15). The insulation layer may cause additional stacking faults to be produced in the surface region (17) of the wafer (15). These defects, namely impurities and stacking faults in the surface region (17) are harmful for the intended operation of the device, and the device will not operate with the predetermined function. Furthermore, manufacturing becomes more expensive because of the requirement of the high temperature and long heating treatment.
There is known another process in which at first a low temperature treatment is performed followed by a high temperarure treatment. But, this process also requires a long time.